TL;DR
UMC and AP Memory announced on October 22, 2026 that their customized S-SiCap Gen2D silicon-capacitor designs completed tape-out and initial functional validation in the third quarter of 2026. Comprehensive system-level performance and reliability testing in substrate packages is still the next step. AI and HPC buyers should treat this as a design-architecture milestone, not as production qualification, guaranteed availability or permission to remove board-level decoupling.
What changed on October 22?
UMC says the collaboration combines its deep-trench-capacitor foundry technology with AP Memory’s silicon-capacitor designs and system-level integration.
The companies describe a shift in power stabilization from the circuit board toward capacitors embedded in an interposer, package substrate or landside location. Placing capacitance closer to the computing die can shorten the power-delivery path, according to UMC.
The announcement confirms tape-out and initial functional validation for S-SiCap Gen2D. It also says comprehensive system-level performance and reliability testing in substrate packages comes next. It does not provide orderable part numbers, unit prices, lead times, package-qualification dates or a mass-production commitment for this specific Gen2D collaboration.
Why does this affect package and PCB sourcing together?
Moving capacitance closer to the die can change the boundary between the semiconductor package and the system PCB. The potential consequences include a revised package ball map, landside keep-outs, BGA escape routing, power and ground via fields, plane structures, the remaining PCB decoupling BOM and the system validation plan.
These effects are design-dependent. The October 22 announcement does not establish that every AI or HPC board can remove conventional capacitors, reduce PCB layers or lower total cost.
Decision gate: confirm the real qualification status
Ask the package or silicon-capacitor supplier to identify the completed and outstanding milestones separately. Distinguish tape-out, initial functional validation, system-level performance testing, reliability testing, package qualification and production release.
A development milestone should not be entered into a sourcing plan as confirmed production availability.
Decision gate: freeze the package-to-board data
Before releasing the PCB, obtain the applicable package model, ball map, electrical limits, capacitance and voltage targets, power-distribution-network impedance requirements, thermal and mechanical constraints, reliability conditions and change-control process.
Then review the complete power path rather than evaluating the package substrate and PCB as unrelated purchases.
Decision gate: compare complete system cost
Cost both the existing and proposed architectures. Include the package or embedded-capacitor premium, component availability, PCB layer and routing changes, the remaining passive BOM, prototype and validation expense, assembly risk and expected production volume.
The supplier announcement does not prove a lower PCBA cost and is not a JETFGO quotation.
Where do JETFGO’s public pages fit?
JETFGO’s public ABF IC substrate page distinguishes package substrates from system-level PCBs and states that substrate projects require project-specific engineering review. Its High Speed PCB page describes review of stack-up, impedance, materials and manufacturing feasibility before production.
Those pages can support an early feasibility discussion. They do not establish that JETFGO has qualified this UMC and AP Memory solution or can manufacture a specific package, substrate or board without reviewing the actual project data.
Bottom line
For an AI or HPC design considering embedded silicon capacitors, keep the PCB release conditional on a frozen package-to-board interface and documented system-level validation status. Initial functional validation is meaningful progress, but it is not yet the final sourcing or production decision.
References
United Microelectronics Corporation, October 22, 2026 https://www.umc.com/en/News/press_release/Content/technology_related/20261022
Related JETFGO pages
ABF IC Substrate https://jetfgo.online/en/products/abf-ic-substrate
High Speed PCB https://jetfgo.online/en/products/high-speed-pcb