TL;DR For a 0.5 mm-pitch package-on-package (PoP) processor, filled via-in-pad is not an automatic requirement. Texas Instruments shows an adjacent-via escape method for a specific PoP design, but the usable method depends on the selected package, pin map and complete board stack-up. Request a design review and comparable construction quotes before choosing the lower-cost route.
Why the question matters
Putting a via directly in a BGA solder pad can improve routing density, but a filled and capped via adds fabrication steps. Moving the via beside the pad may avoid those steps. It can also consume routing space or require another layer, so the lower total PCB price cannot be determined from ball pitch alone.
What the technical example supports
In its June 2010 design guide for a 0.5 mm-pitch PoP applications processor, Texas Instruments illustrates 0.25 mm BGA pads with one 0.082 mm trace and approximately 0.082 mm clearance between adjacent pads. The guide also describes a solder-mask-covered adjacent via for routing inner connections to other layers. It says via-in-pad is generally unnecessary for that 0.5 mm example, while noting that deeper ball rows can require additional routing layers.
Those dimensions describe TI’s worked package and layout, not every 0.5 mm BGA. Its adjacent-via example still calls for laser drilling. Avoiding filled via-in-pad therefore does not necessarily avoid microvias, additional layers or other fabrication costs.
What to decide before quotation
First, confirm the exact component’s current package drawing and assembly guidance. Then ask the PCB designer and fabricator to check whether the required signals, power connections, clearances, via covering and reference planes can be accommodated with adjacent vias.
If both constructions are feasible, request quotes against the same board outline, material, quantity, electrical requirements and acceptance criteria. Compare the complete stack-up, drilling, via filling and capping, layer count, assembly constraints and quoted price. Do not substitute TI’s example dimensions for an approved design rule.
JETFGO’s English 1+N+1 HDI page says BGA fan-out, via-in-pad requirements and the full stack-up are subject to project-specific engineering review. That page is a route for discussing the design; it does not establish that either construction will be feasible or cheaper for a particular order.
References Texas Instruments, PCB Design Guidelines for 0.5mm Package-on-Package Applications Processor, Part I, SPRABB3, June 2010: https://www.ti.com/lit/an/sprabb3/sprabb3.pdf
Related JETFGO pages JETFGO, 1+N+1 HDI Microvia PCB: https://jetfgo.online/en/solutions/hdi-1n1-microvia-pcb